1. Field of the Invention
The invention relates to a failure diagnostic system for a multicore central processing unit (CPU) that is provided with a plurality of CPU cores, and more particularly to a failure diagnostic system that performs a failure diagnosis of each CPU core individually, an electronic control unit (ECU) for a vehicle, and a failure diagnostic method.
2. Description of the Related Art
Mutual abnormality detection is sometimes conducted by detecting abnormality in a LSI or microcomputer by using a configuration in which a plurality of LSI or microcomputers are installed in one system and monitoring a watchdog signal transmitted from one large scale integration (LSI) (microcomputer) to another LSI (microcomputer). Further, in a multicore processor in which one microcomputer carries a plurality of CPU cores, an abnormality is detected by executing the same processing in a plurality of CPU and comparing the processing results. Further, Japanese Patent Application Publication No. 7-230392 (JP-A-7-230392) discloses a method by which a CPU detects abnormality by self-diagnosis.
FIG. 14 is a block-diagram of a processor that conducts self-diagnosis according to JP-A-7-230392. An instruction code generation unit generates an instruction intrinsic code according to an established rule and inputs the code in a code comparison unit. An execution instruction code generation unit generates an instruction intrinsic code according to a rule inverted with respect to that of the instruction code generation unit and inputs the generated instruction intrinsic code into the code comparison unit 4. The code comparison unit compares the two instruction intrinsic codes and detects a failure in the processor if the codes differ from each other.
However, executing the same processing in a plurality of CPU or executing a certain instruction for abnormality detection, as shown in FIG. 14, may put pressure upon resources of the microcomputer or processor, thereby affecting the execution speed of standard processing (reducing the execution speed of standard processing with respect to the usual one) such as control or data processing that is essentially required for the processor.
A conventional multicore processor has a processing mode that is Symmetric Multi-Processing (or called as SMP), a processing mode that is Asymmetric Multiprocessing (or called as AMP), and a processing mode that is Bound Multiprocessing (or called as BMP) combining the SMP and AMP. Further, for example, Japanese Patent Application Publication No. 2008-123439 (JP-A-2008-123439) discloses a processor configured for the BMP mode, wherein when an abnormality occurs in any CPU core, the processing allocated to the CPU core in which the abnormality has occurred is allocated to another CPU core. With the operating system (OS) disclosed in the JP-A-2008-123439, when the processing is allocated to another core, the processing with a high priority order is allocated to a normal CPU and the processing with a low priority order is not performed, thereby making it possible to execute the processing with a high priority order with the same efficiency as that before the abnormality has been detected.
However, the OS disclosed in the JP-A-2008-123439 is not different from that disclosed in JP-A-7-230392 in that a pressure is put upon the resources of microcomputer or processor, for example, a “1+1” addition” is performed by a CPU core, when an abnormality is detected and, therefore, the execution speed of standard processing may be affected.